Record #16301
A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation
Original paper date
Jan 1, 2005
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Open access
No
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0
Same day
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Post-retraction
19
% post-retraction
90.5%
~0.0 citations/yr before retraction · ~0.9 citations/yr after
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